As is well known, a matrix of non-volatile memory cells comprises an array of memory cells arranged in rows and columns, each cell comprising a floating gate MOS transistor and a selection transistor.
Each MOS transistor comprises a drain region and a source region which are integrated in a semiconductor substrate and separated by a substrate portion known as the channel region. A floating gate region is formed above the substrate and separated therefrom by a thin layer of gate oxide. This gate oxide layer has a thinner portion known as the tunnel oxide.
A control gate region is coupled capacitively to the floating gate region through an intermediate dielectric layer known as the interpoly.
A heavily doped region is formed under the tunnel oxide and extends to beneath the drain region. Accordingly, the effective channel region will extend between the source region and this heavily doped region.
A problem with circuits including matrices of EEPROM cells wherein adjacent floating gate transistors have a common source region is that they have effective channel regions of a different length for each adjacent cell. This is due to misalignment of the various masks used at different steps of the process for forming source and drain regions and the heavily doped regions underlying the tunnel oxides.
Another problem encountered in the fabrication of electronic circuits with fast logic transistors and EEPROM matrices integrated in the same die comes from the presence of layers of composite materials, comprising silicon and a transition metal such as titanium or tungsten, known as suicides. These silicide layers are used to provide layers of relatively low resistivity for significantly reducing the resistance of the interconnects and the contacts of individual devices, so that their speed of operation can be improved.
These silicide layers cannot, however, be utilised to fabricate devices wherein the source and drain regions are formed by an LDD implantation technique. For such devices, in fact, the source and drain regions are formed from lightly doped regions.
In detail, the formation of a silicide layer over the active areas of MOS transistors formed with the LDD implantation technique comprises, subsequently to forming the transistor gate, the following steps:
implanting first portions of the source and drain regions at a low dopant concentration; PA1 forming spacers adjacent to the gate and the interconnection lines; PA1 implanting, at a high concentration, second portions contained within the source and drain regions of the transistor; PA1 depositing a transition metal onto the entire surface of the substrate; PA1 applying a thermal process whereby the transition metal is caused to react selectively with the substrate surface to yield silicide in the areas uncovered by dielectric.
The process for forming silicide layers may develop problems in the lightly doped regions due both to the low dopant concentration and small thickness of the latter. For example, in the course of the thermal process for reacting the transition metal layer with the substrate surface, and silicidising the source region of EEPROM cells, a surface layer of the substrate is expended and some of the substrate dopant is taken up in the silicide layer. Consequently, in normal operation of the EEPROM cell, the silicide layer will be shorted to the substrate.